Architecture of 8086 Microprocessor

Internal Architecture of 8086 Microprocessor

8086 microprocessor does not have a RAM or ROM inside it. However, it has internal registers for storing intermediate and final results and interfaces with memory located outside it through the System Bus. 

In the case of 8086, it is a 16-bit Integer processor in a 40-pin, Dual Inline Packaged IC. 

The size of the internal registers(present within the chip) indicates how much information the processor can operate on at a time (in this case 16-bit registers) and how it moves data around internally within the chip, sometimes also referred to as the internal data bus. 

8086 provides the programmer with 14 internal registers, each 16 bits or 2 bytes wide. The main advantage of the 8086 microprocessor is it supports Pipelining.

Pipelining is the process of fetching the next instruction cycle when the current instruction is being executed.

Internal Architecture of 8086 Microprocessor

Memory segmentation:

  • To increase execution speed and fetching speed, 8086 segments the memory.
  • Its 20-bit address bus can address 1MB of memory, it segments it into 16 64kB segments.
  • 8086 works only with four 64KB segments within the whole 1MB memory.

The internal architecture of Intel 8086 is divided into 2 units: The Bus Interface Unit (BIU), and The Execution Unit (EU). These are explained as following below.

1. The Bus Interface Unit (BIU):

It provides the interface of 8086 to external memory and I/O devices via the System Bus. It performs various machine cycles such as memory read, I/O read, etc. to transfer data between memory and I/O devices. 

BIU performs the following functions- 

  • It generates the 20-bit physical address for memory access.
  • It fetches instructions from the memory.
  • It transfers data to and from the memory and I/O.
  • Maintains the 6-byte prefetch instruction queue(supports pipelining).

BIU mainly contains the 4 Segment registers, the Instruction Pointer, a prefetch queue, and an Address Generation Circuit

Instruction Pointer (IP): 

  • It is a 16-bit register. It holds offset of the next instructions in the Code Segment.
  • IP is incremented after every instruction byte is fetched.
  • IP gets a new value whenever a branch instruction occurs.  
  • CS is multiplied by 10H to give the 20-bit physical address of the Code Segment.
  • The address of the next instruction is calculated as CS x 10H + IP.

Example: 

CS = 4321H IP = 1000H 
then CS x 10H = 43210H + offset =  44210H  
Here Offset = Instruction Pointer(IP)

Segment Registers

Segment registers generate memory addresses when combined with other registers in the microprocessor. Segment registers functions differently in real mode and in protected mode operations of the microprocessor.

The minimum size of a segment is 1 byte and maximum size of a segment is 64 Kbytes. A segment begins in memory at a memory address which is divisible by 16.

There are 4 segment registers.

  • CS (Code Segment): It is a section of memory that holds the code (programs and procedures) used by the microprocessor. It defines starting address of the section of memory holding code. In real mode operation, it defines the start of a 64Kb section of memory and in protected mode operation, it selects a descriptor that describes the starting address and length of a section of memory holding code.
  • DS (Data Segment): It is a section of memory that contains data used by a program. The data is accessed in the data segment by an offset address or the contents of other registers that hold the offset address.
  • SS (Stack Segment): It holds the stack of a program which is needed while executing CALL and RET instructions to handle interrupts. Stack entry point is determined by stack segment and stack pointer registers. BP register also addresses data within the stack segment.
  • ES (Extra Segment): It is an additional data segment that is used by some of the string instructions to hold the destination data.

Address Generation Circuit: 

  • The BIU has a Physical Address Generation Circuit.
  • It generates the 20-bit physical address using Segment and Offset addresses using the formula: 
  • in Bus Interface Unit (BIU) circuit shown by the Σ symbol is responsible for the calculation unit which is used to calculate the physical address of an instruction in memory.
     
Physical Address 
= Segment Address x 10H + Offset Address

2. The Execution Unit (EU):

The main components of the EU are General purpose registers, the ALU, Special purpose registers, the Instruction Register and Instruction Decoder, and the Flag/Status Register. 

  1. Fetches instructions from the Queue in BIU, decodes, and executes arithmetic and logic operations using the ALU.
  2. Sends control signals for internal data transfer operations within the microprocessor.(Control Unit)
  3. Sends request signals to the BIU to access the external module.
  4. It operates with respect to T-states (clock cycles) and not machine cycles.

General Purpose Registers

  • AX (Accumulator): AX is addressable as RAX, EAX, AX, AH, or AL. It is used as accumulator which multiply, divide, input/output (I/O) and some of the decimal and ASCII adjustment instructions.
  • BX (Base Index): BX is addressable as RBX, EBX, BX, BH, or BL. It holds the offset address of a location in the memory system. It is also used to refer data in memory.
  • CX (Count): CX is addressable as RCX, ECX, CX, CH, or CL. It holds the count for various instructions and the offset address of memory data. The value of this register indicates the number of times the same instructions has to be executed.
  • DX (Data): DX is addressable as RDX, EDX, DX, DH, or DL. It holds a part of the result from a multiplication or part of the dividend before a division. It also holds the I/O device address while executing the IN and OUT instructions. This register can also address memory data.
  • SP (Stack Pointer): SP is addressable as RSP, ESP, or SP. It is used to hold the offset address of the data stored at the top of stack segment. It is used along with SS register to decide the address at which data is pushed or popped during the execution of PUSH and POP instructions.
  • BP (Base Pointer): BP is addressable as RBP, EBP, or BP. It is used to hold the offset address of data to be read from or write into the stack segment.
  • SI (Source Index): SI is addressable as RSI, ESI, or SI. It is used to hold the offset address of source data in data segment while executing string instructions.
  • DI (Destination Index): DI is addressable as RDI, EDI, or DI. It is used to hold the offset address of destination data in extra segment while executing string instructions.
  • R8 through R15: These registers are only found in the Pentium 4 and Core2 if 64-bit extensions are enabled. The data in these registers are addressed as 64, 32, 16, or 8 – bit sizes and are of general purpose. The 8-bit portion is the rightmost 8-bit only and bits from 8 to 15 are not directly addressable as a byte.

Special-Purpose Registers

The special-purpose registers include RIP, RSP and RFLAGS and the segment registers include CS, DS, ES, SS, FS, and GS.

  • IP (Instruction Pointer): IP is addressable as RIP, EIP or IP. It points to the next instruction in a section of memory defined as a code segment. It is used by microprocessor to find the next sequential instruction in the program located within the code segment.

Flag registers of 8086

The flag registers can be classified into 2 categories,

  1. Status Flags: They indicate the status of the result that is obtained after the execution of the arithmetic or logic instruction.
  2. Control Flags:They can control the operation of CPU.

Status Flags

  • CF (Carry Flag): It holds the carry after addition or borrow after subtraction operation. It also indicates error conditions.
  • PF (Parity Flag): It is the count of ones in a number expressed as even or odd. It is logic 0for odd parity (i.e. odd number of 1s) and logic 1 for even parity (i.e. even number of 1s). For example, if a number contains three binary one bits, it has odd parity and if a number contains no one bits, it has even parity.
  • AF (Auxiliary carry Flag): It holds the carry (half-carry) after addition or borrow after subtraction between bit positions 3 and 4 of the result in a BCD operation. This is used by DAA and DAS instructions to adjust the value in AL after a BCD addition or subtraction, respectively.
  • ZF (Zero Flag):It indicates that the result of an arithmetic or logic operation is zero. If Z=1, the result is zero and if Z= 0, the result is non zero.
  • SF (Sign Flag): It holds the arithmetic sign of the result after arithmetic or logic instruction executes. If S = 1, the sign bit (leftmost bit of a number) is set or negative and if S=0, the sign bit is cleared or positive.
  • TF (Trap Flag): It enables trapping using single step technique. If T flag is set (i.e. TF = 1), 8086 gets interrupted after the execution of each instruction in the program. If TF is cleared (i.e. TF = 0), the trapping or debugging feature is disabled.
  • IF(Interrupt Flag):It controls the operation of the INTR (interrupt request) input pin. If I= 1, the INTR pin is enabled and if I = 0, the INTR pin is disabled. The state of I flag bit is controlled by STI(Set I flag) and CLI (Clear I flag) instructions.
  • DF (Direction Flag): It selects either the increment or decrement mode for the DI and/or SI registers during string instructions. If D = 1, the registers are automatically decremented and if D = 0, the registers are automatically incremented. The D flag is set with the STD(Set Direction) and cleared with the CLD (Clear Direction) instructions.
  • OF (Overflow Flag): It occurs when signed numbers are added or subtracted. Signed numbers are represented in 2’s complement form in microprocessor. It indicates that result has exceeded the capacity of the machine.
  • Example: if the 8-bit signed data 7EH (+126) is added with the 8-bit signed data 02H (+2) then the result is 80H (-128 in 2’s complement form). This result indicates an overflow condition and hence the overflow flag is set during the above signed addition.
  • Note: In an 8-bit register, the minimum and maximum value of the signed number that can be stored is -128 (=80H) and +127 (=7FH) respectively while in a 16 bit register, the minimum and maximum value of the signed number that can be stored is -32768 (=8000H) and +32767 (=7FFFH) respectively.
  • IOPL (I/O Privilege Level): It is used in protected mode operation to select the privilege level for I/O devices. If the current privilege level is higher or more trusted than the IOPL then I/O executes without hindrance. If the current privilege level is lower than the IOPL then an interrupt occurs, causing execution to suspend. An IOPL of 00 is the highest or most trusted and an IOPL of 11 is the lowest or least trusted.
  • NT (Nested Task): It indicates that the current task is nested within another task in protected mode operation. This flag is set when the task is nested by software.
  • RF (Resume Flag): It is used with debugging to control the resumption of execution after the next instruction.
  • VM (Virtual Mode): It selects virtual mode operation in a protected mode system. A virtual mode system allows multiple DOS memory partitions that are 1M byte in length to coexist in the memory. This allows the system program to execute multiple DOS programs.
  • AC (Alignment Check): It activates if a word or double word is addressed on a non-word or non-double word boundary.
  • VIF (Virtual Interrupt Flag): It is a copy of the interrupt flag bit available from Pentium to Pentium 4 microprocessor.
  • VIP (Virtual Interrupt Pending): It provides information about a virtual mode interrupt. It is used in multitasking environments to provide the operating system with virtual interrupt flags and interrupt pending information.
  • ID(Identification): It indicates that the Pentium – Pentium 4 microprocessors support the CPU ID instruction.

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Also Read – Generations of Microprocessor


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